TiN/W/La2O3/Si high-k gate stack for EOT below 0.5nm

P. Ahmet*, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T. Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.

Original languageEnglish
Title of host publicationChina Semiconductor Technology International Conference 2011, CSTIC 2011
Pages99-102
Number of pages4
Edition1
DOIs
StatePublished - 2011
Event10th China Semiconductor Technology International Conference 2011, CSTIC 2011 - Shanghai, China
Duration: 13 Mar 201114 Mar 2011

Publication series

NameECS Transactions
Number1
Volume34
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

Conference10th China Semiconductor Technology International Conference 2011, CSTIC 2011
CountryChina
CityShanghai
Period13/03/1114/03/11

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