Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved with a 3nm W inserted layer after annealed at 800°C in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates for realizing high-k gate stack with EOT of 0.5nm and beyond.
|Title of host publication||China Semiconductor Technology International Conference 2011, CSTIC 2011|
|Number of pages||4|
|State||Published - 2011|
|Event||10th China Semiconductor Technology International Conference 2011, CSTIC 2011 - Shanghai, China|
Duration: 13 Mar 2011 → 14 Mar 2011
|Conference||10th China Semiconductor Technology International Conference 2011, CSTIC 2011|
|Period||13/03/11 → 14/03/11|