Timing jitter and modulation profile extraction for spread-spectrum clocks

Jenchien Hsu*, Chau-Chin Su

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations


This paper presents a built-in jitter measurement approach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach. Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is proposed to correlate SSC and non-SSC jitter. A 1.2-GHz eight-phase SSC generator with the jitter measurement circuit is designed and fabricated using the 0.18-μm complementary metaloxidesemiconductor technology. The measured results are validated by the proposed estimation method, which is the key contribution of this paper. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026 UI.

Original languageEnglish
Article number5256211
Pages (from-to)847-856
Number of pages10
JournalIEEE Transactions on Instrumentation and Measurement
Issue number4
StatePublished - 1 Apr 2010


  • Analog testing
  • Built-in self test
  • Jitter
  • Jitter measurement
  • Phase-locked loop (PLL)
  • Spread-spectrum clock (SSCs)

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