Timing driven partition for multi-FPGA systems with TDM awareness

Sin Hong Liou; Sean Liu; Richard Sun; Hung Ming Chen

doi:10.1145/3372780.3375558

Timing driven partition for multi-FPGA systems with TDM awareness

Sin Hong Liou, Sean Liu, Richard Sun, Hung Ming Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. To overcome the connectivity constraint between each pair of FPGAs, Time-division multiplexing (TDM) is adopted with the expense of additional delay that dominates the performance on multi-FPGA system based emulator. To the best of our knowledge, there is no prior work on partitioning for multi-FPGA system considering hardware configuration and the impact of TDM. This work proposes a partition methodology to improve timing performance for multi-FPGA system. Delay introduced by TDM is estimated and optimized using look-up table for better efficiency. Our experimental result shows 43% improvement in maximum delay while considering both hardware configuration and impact of TDM compared with cut driven partition approach.

Original language	English
Title of host publication	ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design
Publisher	Association for Computing Machinery
Pages	111-118
Number of pages	8
ISBN (Electronic)	9781450370912
DOIs	https://doi.org/10.1145/3372780.3375558
State	Published - 20 Sep 2020
Event	23rd International Symposium on Physical Design, ISPD 2020 - Taipei, Taiwan Duration: 29 Mar 2020 → 1 Apr 2020

Publication series

Name	Proceedings of the International Symposium on Physical Design

Conference

Conference	23rd International Symposium on Physical Design, ISPD 2020
Country	Taiwan
City	Taipei
Period	29/03/20 → 1/04/20

Keywords

Field programmable gate array
Partitioning
Physical design
Time-division-multiplexing

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10.1145/3372780.3375558

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title = "Timing driven partition for multi-FPGA systems with TDM awareness",

abstract = "Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. To overcome the connectivity constraint between each pair of FPGAs, Time-division multiplexing (TDM) is adopted with the expense of additional delay that dominates the performance on multi-FPGA system based emulator. To the best of our knowledge, there is no prior work on partitioning for multi-FPGA system considering hardware configuration and the impact of TDM. This work proposes a partition methodology to improve timing performance for multi-FPGA system. Delay introduced by TDM is estimated and optimized using look-up table for better efficiency. Our experimental result shows 43% improvement in maximum delay while considering both hardware configuration and impact of TDM compared with cut driven partition approach.",

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language = "English",

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Liou, SH, Liu, S, Sun, R & Chen, HM 2020, Timing driven partition for multi-FPGA systems with TDM awareness. in ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Proceedings of the International Symposium on Physical Design, Association for Computing Machinery, pp. 111-118, 23rd International Symposium on Physical Design, ISPD 2020, Taipei, Taiwan, 29/03/20. https://doi.org/10.1145/3372780.3375558

Timing driven partition for multi-FPGA systems with TDM awareness. / Liou, Sin Hong; Liu, Sean; Sun, Richard; Chen, Hung Ming.

ISPD 2020 - Proceedings of the 2020 International Symposium on Physical Design. Association for Computing Machinery, 2020. p. 111-118 (Proceedings of the International Symposium on Physical Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Multi-FPGA system is a popular approach to achieve hardware acceleration with the scalability to accommodate large designs. To overcome the connectivity constraint between each pair of FPGAs, Time-division multiplexing (TDM) is adopted with the expense of additional delay that dominates the performance on multi-FPGA system based emulator. To the best of our knowledge, there is no prior work on partitioning for multi-FPGA system considering hardware configuration and the impact of TDM. This work proposes a partition methodology to improve timing performance for multi-FPGA system. Delay introduced by TDM is estimated and optimized using look-up table for better efficiency. Our experimental result shows 43% improvement in maximum delay while considering both hardware configuration and impact of TDM compared with cut driven partition approach.

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Timing driven partition for multi-FPGA systems with TDM awareness

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Conference

Keywords

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