Timing and power fluctuations on gate-all-around nanowire CMOS circuit induced by various sources of random discrete dopants

Wen Li Sung, Pei Jung Chao, Yiming Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Random dopant fluctuation (RDF) is one of fluctuation sources in sub-7-nm semiconductor technology node. In this paper, we estimate the timing and power fluctuations on 10-nm-gate gate-all-around (GAA) silicon nanowire (NW) complementary metal-oxide-semiconductor (CMOS) circuit induced by various random discrete dopants (RDDs) from channel (with/without doping), source/drain (S/D) extensions and penetration from S/D extensions. The 3D quantum mechanical transport and non-equilibrium Green's function (NEGF) models were used for the NW CMOS circuit. The experimentally validated device simulation indicates that at a similar threshold voltage, CMOS devices without channel doping possess 49.5% reduction on the normalized fluctuation of the static power consumption due to the reduction of σVth and σIoff. The normalized fluctuation of dynamic power is comparable with/without channel doping due to small variation of the gate capacitance. Because of reduction of σIsat, the normalized fluctuation of short-circuit power of CMOS circuit was reduced from 21.7% to 10.2% without channel doping. And, we found that the fluctuations of the timing, noise margin (NM) and power consumption of the NW CMOS circuit follow the trend of σVth. From the point of view of N-/P-type NW MOSFETs caused by RDF, this study may show the fluctuation of CMOS circuit performance highly influenced by the key parameters of N-/P-type NW MOSFETs.

Original languageEnglish
Title of host publication2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages61-64
Number of pages4
ISBN (Electronic)9784863486102
DOIs
StatePublished - 25 Oct 2017
Event2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 - Kamakura, Japan
Duration: 7 Sep 20179 Sep 2017

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume2017-September

Conference

Conference2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
CountryJapan
CityKamakura
Period7/09/179/09/17

Keywords

  • CMOS circuit
  • gate-all- A round
  • nanowire
  • power fluctuation
  • Timing fluctuation

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