Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)

Kyuchul Chong*, Xi Zhang, King-Ning Tu, Daquan Huang, Mau-Chung Chang, Ya Hong Xie

*Corresponding author for this work

Research output: Contribution to journalArticle

8 Scopus citations


A novel approach for three-dimensional substrate impedance engineering of p-/p+ Si substrate is described for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to radio frequency (RF) crosstalk via substrate and on-chip inductor performance. Electroless plating or electro-plating is used to fabricate Faraday cage for crosstalk isolation as well as to provide "true ground" contacts. A self-limiting porous Si (PS) formation process is employed to allow the insertion of PS regions from the backside of the wafer, eliminating completely the waste of chip surface area. On-chip inductors are situated above the semi-insulating PS regions allowing for greatly increased Q-factor and resonance frequency (fr). RF crosstalk is reduced to the level limited by that across the air gap between the measurement probes.

Original languageEnglish
Pages (from-to)2440-2446
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number11
StatePublished - 1 Nov 2005


  • Crosstalk
  • Mixed-signal system-on-chip (SoC)
  • On-chip inductor
  • Porous Si
  • Radio frequency (RF) isolation

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