Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

Yiming Li*, Bo Shian Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

In this paper, a three-dimensional simulation of single-, double-, and surrounding-gate polysilicon thin film transistors (TFTs) is presented. Grain trap model is considered in the transport model. Calculations of the driving current, ID-VD and ID-VG curves are performed. Among three device structures, polysilicon TFTs with surrounding-gate structure reduce the leakage current and improve the short channel effects due to the excellent infinite-gate channel controllability.

Original languageEnglish
Pages86-89
Number of pages4
StatePublished - 2006
Event2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
Duration: 7 May 200611 May 2006

Conference

Conference2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
CountryUnited States
CityBoston, MA
Period7/05/0611/05/06

Keywords

  • Double-gate
  • Modeling and simulation
  • Polysilicon TFTs
  • Single-gate
  • Surrounding-gate

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