Three-dimensional simulation of nanoscale copper interconnects

Hung Mu Chou*, Yiming Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Copper (Cu) interconnects are one of promising approaches for design and fabrication of gigascale ultra-large scale integrated (ULSI) circuit. In this paper, three configurations of interconnect, the parallel lines, the parallel lines on a plane, and the parallel lines between two planes are investigated. Three-dimensional simulation is performed by solving an electrostatic model using adaptive computing technique. For the studied three configurations, delay of resistance and capacitance (RC) is calculated with respect to different line spacing, line distance to plane, line width, and line height. Equivalent circuit is implemented for circuit simulation, and calculation of timing delay and crosstalk. It is found that RC time constant not only depends on the configurations but also dominates by the ratio of line height to line width. For sub-100 nm fabrication technology, there is an optimal design with respect to the three configurations. If the ratio of line height to line width is larger than 1, the RC time constant reaches to a minimum.

Original languageEnglish
Title of host publication2005 5th IEEE Conference on Nanotechnology
PublisherIEEE Computer Society
Pages721-724
Number of pages4
ISBN (Print)0780391993, 9780780391994
DOIs
StatePublished - 2005
Event2005 5th IEEE Conference on Nanotechnology - Nagoya, Japan
Duration: 11 Jul 200515 Jul 2005

Publication series

Name2005 5th IEEE Conference on Nanotechnology
Volume2

Conference

Conference2005 5th IEEE Conference on Nanotechnology
CountryJapan
CityNagoya
Period11/07/0515/07/05

Keywords

  • Circuit
  • Devices
  • Interconnection
  • Modeling and simulation
  • Nanoelectronics
  • RC time constant

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