Three-dimensional metal gate-high-Κ-GOI CMOSFETs on 1-poly-6-metal 0.18-μm Si devices

D. S. Yu*, Albert Chin, C. C. Liao, C. F. Lee, C. F. Cheng, M. F. Li, Won Jong Yoo, S. P. McAlister

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

We demonstrate three-dimensional (3-D) self-aligned [IrO2-IrO2-Hf]-LaAlO3-Ge-on-insulator (GOI) CMOSFETs above 0.18-μm Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO2-LaAlO 3-GOI p-MOSFETs and IrO2-Hf-LaAlO 3-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm2/Vs respectively, without depredating the underneath 0.18-μm Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.

Original languageEnglish
Pages (from-to)118-120
Number of pages3
JournalIEEE Electron Device Letters
Volume26
Issue number2
DOIs
StatePublished - 1 Feb 2005

Keywords

  • Ge-on-insulator (GOI)
  • LaA1O
  • Metal-gate
  • MOSFET
  • Three-dimensional (3-D)

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