Three-dimensional impedance engineering for mixed-signal system-on-chip applications

Kyuchul Chong*, Xi Zhang, King-Ning Tu, Daquan Huang, Mau-Chung Chang, Ya Hong Xie

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p-/p+ Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2005 Custom Integrated Circuits Conference
Pages658-661
Number of pages4
DOIs
StatePublished - 1 Dec 2005
EventIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 18 Sep 200521 Sep 2005

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2005
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2005 Custom Integrated Circuits Conference
CountryUnited States
CitySan Jose, CA
Period18/09/0521/09/05

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