Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling

Qun Gu; Zhiwei Xu; Jongsun Kim; Jenwei Ko; Mau-Chung Chang

doi:10.1109/VLSIT.2004.1345414

Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling

Qun Gu^*, Zhiwei Xu, Jongsun Kim, Jenwei Ko, Mau-Chung Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18μm CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2×10 ^-10 and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm ² chip area.

Original language	English
Pages (from-to)	96-97
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2004.1345414
State	Published - 1 Oct 2004
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: 15 Jun 2004 → 17 Jun 2004

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title = "Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling",

abstract = " A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18μm CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2×10 -10 and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm 2 chip area. ",

author = "Qun Gu and Zhiwei Xu and Jongsun Kim and Jenwei Ko and Mau-Chung Chang",

year = "2004",

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doi = "10.1109/VLSIT.2004.1345414",

language = "English",

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journal = "Digest of Technical Papers - Symposium on VLSI Technology",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 15-06-2004 Through 17-06-2004",

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T1 - Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling

AU - Gu, Qun

AU - Xu, Zhiwei

AU - Kim, Jongsun

AU - Ko, Jenwei

AU - Chang, Mau-Chung

PY - 2004/10/1

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N2 - A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18μm CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2×10 -10 and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm 2 chip area.

AB - A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18μm CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2×10 -10 and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm 2 chip area.

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JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

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