Thread allocation in chip multiprocessor based multithreaded network processors

Yi Neng Lin*, Ying-Dar Lin, Yuan Chen Lai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This work tries to derive ideas for thread allocation in Chip Multiprocessor (CMP)-based network processors performing general applications by Continuous-Time Markov Chain modeling and Petri net simulations. The concept of P-M ratio, where P and M indicate the computational and memory access overhead when processing a packet, is introduced and the relation to thread allocation is explored. Results indicate that the demand of threads in a processor diminishes rapidly as P-M ratio increases to 0.066, and decreases slowly afterwards. Observations from a certain P-M ratio can be applied to various software-hardware combinations having the same ratio.

Original languageEnglish
Title of host publicationProceedings - 22nd International Conference on Advanced Information Networking and Applications, AINA 2008
Pages718-725
Number of pages8
DOIs
StatePublished - 1 Sep 2008
Event22nd International Conference on Advanced Information Networking and Applications, AINA 2008 - Gino-wan, Okinawa, Japan
Duration: 25 Mar 200828 Mar 2008

Publication series

NameProceedings - International Conference on Advanced Information Networking and Applications, AINA
ISSN (Print)1550-445X

Conference

Conference22nd International Conference on Advanced Information Networking and Applications, AINA 2008
CountryJapan
CityGino-wan, Okinawa
Period25/03/0828/03/08

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    Lin, Y. N., Lin, Y-D., & Lai, Y. C. (2008). Thread allocation in chip multiprocessor based multithreaded network processors. In Proceedings - 22nd International Conference on Advanced Information Networking and Applications, AINA 2008 (pp. 718-725). [4482777] (Proceedings - International Conference on Advanced Information Networking and Applications, AINA). https://doi.org/10.1109/AINA.2008.50