Thin gate oxides promise high reliability

Chen-Ming Hu*, Donggun Park, Ya Chin King

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The limiting factor for gate oxide scaling will be device speed turnaround because of mobility loss. The optimal thickness of SiO2 for speed considerations is 2 nm, which should be sufficient for channel lengths down to 50 nm. Where scaling below 1.5 nm is desired, alternative dielectrics will have to be considered.

Original languageEnglish
Pages (from-to)215-222
Number of pages8
JournalSemiconductor International
Volume21
Issue number8
StatePublished - 1 Jul 1998

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