Plasma processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modelled as damage produced by constant-current (or voltage) electrical stress. Plasma processing causes MOSFET parameter degradation, from which one can deduce the plasma charging current. Since the scattering of post-damage device parameters is due to a reproducible variation of stress current across the wafer, one can easily analyse the effect of device geometry on damage by comparing test structures in the same die rather than the averages over a wafer. We have developed a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of the charging current. The model successfully predicts the oxide thickness dependence of plasma charging. It is shown that plasma acting on a very thin oxide during processing may be modelled essentially as a current source. Thus the damage will not be greatly exacerbated as the oxide thickness is further reduced in the future. Although annealing in forming gas can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. The protection diode should be forward biased during processing to safely protect the gate oxide. In CMOS circuits, the drains of the driver circuit can generally act as adequate protection diodes for the oxide regardless of N or P substrate and the polarity of the plasma charging current. The plasma stress current can be reduced by reducing the ion density, which is unfortunately linked to the etch rate or directionality, or by reducing the electron temperature. Maintaining a very uniform plasma over the surface of the wafer, reducing the plasma charging current during the over-etch time and judicious use of protection diode and antenna design rules will reduce plasma damage to an acceptable level for ULSI production even for very thin gate oxides.