Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors

M. F. Wang*, Y. C. Kao, T. Y. Huang, Horng-Chih Lin, C. Y. Chang

*Corresponding author for this work

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n + /p junctions need higher thermal budget than p + /n junctions to achieve low leakage performance. It was also found from C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.

Original languageEnglish
Pages36-39
Number of pages4
DOIs
StatePublished - 1 Jan 2001
Event6th International Symposium on Plasma- and Process-Induced Damage - Monterrrey, CA, United States
Duration: 13 May 200115 May 2001

Conference

Conference6th International Symposium on Plasma- and Process-Induced Damage
CountryUnited States
CityMonterrrey, CA
Period13/05/0115/05/01

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    Wang, M. F., Kao, Y. C., Huang, T. Y., Lin, H-C., & Chang, C. Y. (2001). Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors. 36-39. Paper presented at 6th International Symposium on Plasma- and Process-Induced Damage, Monterrrey, CA, United States. https://doi.org/10.1109/PPID.2001.929973