The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n + /p junctions need higher thermal budget than p + /n junctions to achieve low leakage performance. It was also found from C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.
|Number of pages||4|
|State||Published - 1 Jan 2001|
|Event||6th International Symposium on Plasma- and Process-Induced Damage - Monterrrey, CA, United States|
Duration: 13 May 2001 → 15 May 2001
|Conference||6th International Symposium on Plasma- and Process-Induced Damage|
|Period||13/05/01 → 15/05/01|