Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

Chih Yuan Chang; Po-Tsang Huang; Yi Chun Chen; Tian-Sheuan Chang; Wei Hwang

doi:10.1109/SOCC.2014.6948903

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

Chih Yuan Chang, Po-Tsang Huang, Yi Chun Chen, Tian-Sheuan Chang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

Original language	English
Title of host publication	International System on Chip Conference
Editors	Ramalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
Publisher	IEEE Computer Society
Pages	76-81
Number of pages	6
ISBN (Electronic)	9781479933785
DOIs	https://doi.org/10.1109/SOCC.2014.6948903
State	Published - 5 Nov 2014
Event	27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States Duration: 2 Sep 2014 → 5 Sep 2014

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	27th IEEE International System on Chip Conference, SOCC 2014
Country	United States
City	Las Vegas
Period	2/09/14 → 5/09/14

Access to Document

10.1109/SOCC.2014.6948903

Link to publication in Scopus

Fingerprint Dive into the research topics of 'Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video'. Together they form a unique fingerprint.

Cite this

Chang, C. Y., Huang, P-T., Chen, Y. C., Chang, T-S., & Hwang, W. (2014). Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. In R. Sridhar, D. Zhao, K. Shi, & T. Buchner (Eds.), International System on Chip Conference (pp. 76-81). [6948903] (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2014.6948903

Chang, Chih Yuan ; Huang, Po-Tsang ; Chen, Yi Chun ; Chang, Tian-Sheuan ; Hwang, Wei. / Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. International System on Chip Conference. editor / Ramalingam Sridhar ; Danella Zhao ; Kaijian Shi ; Thomas Buchner. IEEE Computer Society, 2014. pp. 76-81 (International System on Chip Conference).

@inproceedings{69b0840fd1774dd7951120271216152c,

title = "Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video",

abstract = "With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.",

author = "Chang, {Chih Yuan} and Po-Tsang Huang and Chen, {Yi Chun} and Tian-Sheuan Chang and Wei Hwang",

year = "2014",

month = nov,

day = "5",

doi = "10.1109/SOCC.2014.6948903",

language = "English",

series = "International System on Chip Conference",

publisher = "IEEE Computer Society",

pages = "76--81",

editor = "Ramalingam Sridhar and Danella Zhao and Kaijian Shi and Thomas Buchner",

booktitle = "International System on Chip Conference",

note = "null ; Conference date: 02-09-2014 Through 05-09-2014",

}

Chang, CY, Huang, P-T, Chen, YC, Chang, T-S & Hwang, W 2014, Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. in R Sridhar, D Zhao, K Shi & T Buchner (eds), International System on Chip Conference., 6948903, International System on Chip Conference, IEEE Computer Society, pp. 76-81, 27th IEEE International System on Chip Conference, SOCC 2014, Las Vegas, United States, 2/09/14. https://doi.org/10.1109/SOCC.2014.6948903

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. / Chang, Chih Yuan; Huang, Po-Tsang; Chen, Yi Chun; Chang, Tian-Sheuan ; Hwang, Wei.

International System on Chip Conference. ed. / Ramalingam Sridhar; Danella Zhao; Kaijian Shi; Thomas Buchner. IEEE Computer Society, 2014. p. 76-81 6948903 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video

AU - Chang, Chih Yuan

AU - Huang, Po-Tsang

AU - Chen, Yi Chun

AU - Chang, Tian-Sheuan

AU - Hwang, Wei

PY - 2014/11/5

Y1 - 2014/11/5

N2 - With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

AB - With the increasing resolution of 3D high definition (HD) video, high bandwidth, large capability, low power memory becomes essential. In this paper, a thermal-aware hierarchal memory management unit (MMU) in a 3D-Stacked DRAM model is proposed for 3D HD video systems. By constructing the 4Gb, 4-stack 3D DDR3 DRAM model with through-silicon-vias (TSVs), the data bandwidth can be up to 21.3 GB/s @ 333MHz. Additionally, an efficient address translator, a global rank controller and local slice controllers are proposed in the hierarchal MMU for 3D Full HD video disparity calculation. The hierarchal MMU can improve bandwidth by 54.3% through command reordering and bank/rank interleaving. Moreover, power reduction of up to 43.46% can be realized in low power mode by the dynamic thermal-aware refresh timing control and deep power down detection.

UR - http://www.scopus.com/inward/record.url?scp=84911942046&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2014.6948903

DO - 10.1109/SOCC.2014.6948903

M3 - Conference contribution

AN - SCOPUS:84911942046

T3 - International System on Chip Conference

SP - 76

EP - 81

BT - International System on Chip Conference

A2 - Sridhar, Ramalingam

A2 - Zhao, Danella

A2 - Shi, Kaijian

A2 - Buchner, Thomas

PB - IEEE Computer Society

Y2 - 2 September 2014 through 5 September 2014

ER -