Thermal annealing, interface reaction, and lanthanum-based sub-nanometer EOT gate dielectrics

Hei Wong*, Jieqiong Zhang, Shurong Dong, Kuniyuki Kakushima, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


In future nanoscale complementary metal-oxide-semiconductor (CMOS) devices, the high dielectric constant (high-k) gate dielectric film will be shrunk down to a couple of nanometers or down to the sub-nanometer range in the sense of oxide equivalent thickness (EOT). However, as high-k materials, including La2O3 which has been considered to be one of the promising next generation gate dielectric materials, are only marginally stable on the silicon substrate, some nominal temperature processes used for the device fabrication may still give rise to interface reactions and result in a low-k interface layer which will be a critical constraint for achieving the ultrathin EOT gate dielectric film. In this work, some issues related to the material interaction at the lanthanum oxide/Si and lanthanum oxide/metal interfaces will be discussed with the supports of interface bonding structures as revealed by using angle-resolved x-ray photoelectron spectroscopy (ARXPS) measurements. We show that thermal annealing at temperature above 500°C would result in the migration of Si atoms deep into the bulk of the La2O3 film and formation of silicate phases both at the interface and in the bulk. These effects would significantly lower the dielectric constant and thus increases the effective thickness of the dielectric film from the equivalent silicon oxide thickness (EOT) point of view.

Original languageEnglish
Pages (from-to)2-7
Number of pages6
StatePublished - 1 Aug 2015


  • CMOS technology
  • High-k
  • Interface structure
  • Lanthanum oxide

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