Theoretical analysis for low-power test decompression using test-slice duplication

Szu Pang Mu*, Chia-Tso Chao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Pages147-152
Number of pages6
DOIs
StatePublished - 29 Jun 2010
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: 19 Apr 201022 Apr 2010

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference28th IEEE VLSI Test Symposium, VTS10
CountryUnited States
CitySanta Cruz, CA
Period19/04/1022/04/10

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  • Cite this

    Mu, S. P., & Chao, C-T. (2010). Theoretical analysis for low-power test decompression using test-slice duplication. In Proceedings - 28th IEEE VLSI Test Symposium, VTS10 (pp. 147-152). [5469591] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2010.5469591