A new physical timing model for small-geometry CMOS inverters with interconnection lines has been developed. Large-signal equivalent circuits of CMOS inverters and 10-section R C ladder networks for interconnection lines are considered together with nonstep input waveforms and initial delay times. Due to more realistic and complete considerations, the model accuracy is expected to be higher than the conventional delay models. Extensive comparisons between model calculations and SPICE simulations have shown that the model has a maximum relative error of 16% on the delay times of CMOS inverters with interconnection lines of different R and C values and section numbers N, different gate sizes, device parameters, and even input excitation waveforms. Reasonable accuracy, wide applicable range, and high computation efficiency make the developed timing models quite attractive in MOS VLSI timing verification and auto-sizing.