LDD MOSFET's with a high dielectric spacer has been proposed to improve the devices' performance El]. This improvement is attributed to the conductivity modulation effect on the the lightly doped source/drain region from enhanced fringe field through high dielectric spacer. However, to reduce the stress of high dielectric spacer on the silicon, the oxide layers on Si and poly-Si are not etched compIetely before the spacer deposition. In this paper these two oxide layers are called the spacer bottom oxide and the sidewall poly oxide ,respectively. By using the 2-0 device simulator 1121, we have comprehensively studied the impact of sidewall poly oxide and spacer bottom oxide on the driving current capability of sub-pm LDD MOSFET's. For the first-time, we report that reducing thickness of sidewall poly oxide and spacer bottom oxide will improve the devices' performance significantly, as the MOSFETgate length scales down to sub-0.5μm regime.