The role of a resist during O2 plasma ashing and its impact on the reliability evaluation of ultrathin gate oxides

Chao-Hsin Chien*, Chun Yen Chang, Horng-Chih Lin, Tsai Fu Chang, Szu Kang Hsien, Hua Chou Tseng, Shean Guang Chiou, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm. becomes significant as the oxide thickness is scaled down below 6nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.

Original languageEnglish
Pages (from-to)4866-4873
Number of pages8
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number7 SUPPL. B
StatePublished - 1 Jul 1997


  • Ashing
  • Degradation
  • Overashing
  • Overlayer
  • Resist

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