The process and stress-induced variability issues of trigate CMOS devices

Steve S. Chung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Not only the popular random dopant fluctuation (RDF), but also the traps, caused by the hot carrier stress induce the Vth variations. This paper will address the importance of these effects and the experimental demonstration of the process- and trap-induced fluctuations. The boron clustering, sidewall roughness, and the electrical stress effects can all be justified by the theory and the method. This method provides us a valuable tool for the understanding of the process and stress induced variability in 3D devices (e.g., FinFET).

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
StatePublished - 23 Dec 2013
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
Duration: 3 Jun 20135 Jun 2013

Publication series

Name2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Conference

Conference2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CountryHong Kong
CityHong Kong
Period3/06/135/06/13

Keywords

  • Reliability
  • Trigate CMOS
  • Variability
  • Variation

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