The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications

Wei Chen Chen*, Horng-Chih Lin, Tiao Yuan Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (lDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.

Original languageEnglish
Title of host publication2010 Silicon Nanoelectronics Workshop, SNW 2010
DOIs
StatePublished - 22 Oct 2010
Event2010 15th Silicon Nanoelectronics Workshop, SNW 2010 - Honolulu, HI, United States
Duration: 13 Jun 201014 Jun 2010

Publication series

Name2010 Silicon Nanoelectronics Workshop, SNW 2010

Conference

Conference2010 15th Silicon Nanoelectronics Workshop, SNW 2010
CountryUnited States
CityHonolulu, HI
Period13/06/1014/06/10

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  • Cite this

    Chen, W. C., Lin, H-C., & Huang, T. Y. (2010). The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications. In 2010 Silicon Nanoelectronics Workshop, SNW 2010 [5562550] (2010 Silicon Nanoelectronics Workshop, SNW 2010). https://doi.org/10.1109/SNW.2010.5562550