The performance and reliability enhancement of ETOX p-channel Flash EEPROM cell with p-doped floating-gate

H. W. Tsai, P. Y. Chiang, Steve S. Chung, D. S. Kuo, M. S. Liang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we proposed a simple approach for designing reliable and high performance p-channel Flash EEPROM cell from the floating-gate engineering point of view. In other words, a p-type doped floating gate used in a p-channel flash cell can achieve this goal. Results show that the programming speed, gate/drain disturb, read lifetime, and data retention in p-type floating-gate cell are much better than those of n-type floating-gate cell; except that p-type floating-gate cell has slower erasing speed. These results can be used as a guideline for designers to choose.

Original languageEnglish
Title of host publicationVLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages36-39
Number of pages4
ISBN (Electronic)0780377656
DOIs
StatePublished - 1 Jan 2003
Event20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 - Hsinchu, Taiwan
Duration: 6 Oct 20038 Oct 2003

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume2003-January
ISSN (Print)1930-8868

Conference

Conference20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003
CountryTaiwan
CityHsinchu
Period6/10/038/10/03

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