The issues on the power consumption of Trigate FinFET: The design and manufacturing guidelines

Steve S. Chung, E. R. Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.

Original languageEnglish
Title of host publication24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538617793
DOIs
StatePublished - 5 Oct 2017
Event24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 - Chengdu, China
Duration: 4 Jul 20177 Jul 2017

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2017-July

Conference

Conference24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
CountryChina
CityChengdu
Period4/07/177/07/17

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    Chung, S. S., & Hsieh, E. R. (2017). The issues on the power consumption of Trigate FinFET: The design and manufacturing guidelines. In 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 (pp. 1-4). (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2017-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2017.8060064