The intrinsic parameter fluctuation on high-κ/metal gate bulk FinFET devices

Yiming Li*, Hsin Wen Su, Yu Yu Chen, Sheng Chia Hsu, Wen Tsung Huang

*Corresponding author for this work

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFET, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature.

Original languageEnglish
Pages (from-to)302-305
Number of pages4
JournalMicroelectronic Engineering
Volume109
DOIs
StatePublished - 2013

Keywords

  • 16-nm-gate
  • Bulk FinET
  • Characteristic fluctuation
  • Random discrete dopant
  • Random interface trap
  • Random work function
  • Statistical 3D device simulation

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