The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

Tian-Li Wu*, Denis Marcon, Brice De Jaeger, Marleen Van Hove, Benoit Bakeroot, Dennis Lin, Steve Stoffels, Xuanwu Kang, Robin Roelofs, Guido Groeseneken, Stefaan Decoutere

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (VTH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.

Original languageEnglish
Title of host publication2015 IEEE 27th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages225-228
Number of pages4
ISBN (Electronic)9781479962594
DOIs
StatePublished - 12 Jun 2015
Event27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015 - Hong Kong, China
Duration: 10 May 201514 May 2015

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
Volume2015-June
ISSN (Print)1063-6854

Conference

Conference27th IEEE International Symposium on Power Semiconductor Devices and IC's, ISPSD 2015
CountryChina
CityHong Kong
Period10/05/1514/05/15

Keywords

  • AlGaN/GaN
  • border traps
  • depletion mode
  • enhacement mode
  • gate dielectric
  • interface states
  • PE-ALD SiN
  • recessed gate

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