The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

Steve S. Chung*, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen, M. S. Liang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V T shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV T in thin-oxide with reduced width.

Original languageEnglish
Pages279-282
Number of pages4
StatePublished - 1 Dec 2004
EventProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan
Duration: 5 Jul 20048 Jul 2004

Conference

ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
CountryTaiwan
Period5/07/048/07/04

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