The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

Steve S. Chung; C. H. Yeh; S. J. Feng; C. S. Lai; J. J. Yang; C. C. Chen; Y. Jin; S. C. Chen; M. S. Liang

The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

Steve S. Chung^*, C. H. Yeh, S. J. Feng, C. S. Lai, J. J. Yang, C. C. Chen, Y. Jin, S. C. Chen, M. S. Liang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I _D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I _D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V _T shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV _T in thin-oxide with reduced width.

Original language	English
Pages	279-282
Number of pages	4
State	Published - 1 Dec 2004
Event	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan Duration: 5 Jul 2004 → 8 Jul 2004

Conference

Conference	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country	Taiwan
Period	5/07/04 → 8/07/04

Fingerprint Dive into the research topics of 'The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology'. Together they form a unique fingerprint.

Cite this

Chung, S. S., Yeh, C. H., Feng, S. J., Lai, C. S., Yang, J. J., Chen, C. C., Jin, Y., Chen, S. C., & Liang, M. S. (2004). The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology. 279-282. Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.

Chung, Steve S. ; Yeh, C. H. ; Feng, S. J. ; Lai, C. S. ; Yang, J. J. ; Chen, C. C. ; Jin, Y. ; Chen, S. C. ; Liang, M. S. / The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology. Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.4 p.

@conference{aca7c4dbd56d4a358b8705e4a3bee780,

title = "The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology",

abstract = " In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V T shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV T in thin-oxide with reduced width.",

author = "Chung, {Steve S.} and Yeh, {C. H.} and Feng, {S. J.} and Lai, {C. S.} and Yang, {J. J.} and Chen, {C. C.} and Y. Jin and Chen, {S. C.} and Liang, {M. S.}",

year = "2004",

month = dec,

day = "1",

language = "English",

pages = "279--282",

note = "null ; Conference date: 05-07-2004 Through 08-07-2004",

}

Chung, SS, Yeh, CH, Feng, SJ, Lai, CS, Yang, JJ, Chen, CC, Jin, Y, Chen, SC & Liang, MS 2004, 'The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology', Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan, 5/07/04 - 8/07/04 pp. 279-282.

The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology. / Chung, Steve S.; Yeh, C. H.; Feng, S. J.; Lai, C. S.; Yang, J. J.; Chen, C. C.; Jin, Y.; Chen, S. C.; Liang, M. S.

2004. 279-282 Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology

AU - Chung, Steve S.

AU - Yeh, C. H.

AU - Feng, S. J.

AU - Lai, C. S.

AU - Yang, J. J.

AU - Chen, C. C.

AU - Jin, Y.

AU - Chen, S. C.

AU - Liang, M. S.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V T shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV T in thin-oxide with reduced width.

AB - In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V T shifts are significant, The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage current and an increase of ΔV T in thin-oxide with reduced width.

UR - http://www.scopus.com/inward/record.url?scp=14844312909&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:14844312909

SP - 279

EP - 282

Y2 - 5 July 2004 through 8 July 2004

ER -