The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

Wei Jen Chang*, Ming-Dou Ker, Tai Xiang Lai, Tien Hao Tang, Kuan Cheng Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
Pages249-252
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India
Duration: 11 Jul 200713 Jul 2007

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
CountryIndia
CityBangalore
Period11/07/0713/07/07

Fingerprint Dive into the research topics of 'The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process'. Together they form a unique fingerprint.

Cite this