The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices

Wen Tsung Huang, Yiming Li*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.

Original languageEnglish
Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages281-284
Number of pages4
ISBN (Electronic)9781479952885
DOIs
StatePublished - 20 Oct 2014
Event2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, Japan
Duration: 9 Sep 201411 Sep 2014

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
CountryJapan
CityYokohama
Period9/09/1411/09/14

Keywords

  • fin-LER
  • gateLER
  • line edge roughness
  • sidewall-LER
  • trapezoidal bulk FinFET

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