The impact of device scaling and power supply change on CMOS gate performance

Kai Chen*, H. Clement Wann, Ping K. Ko, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

44 Scopus citations

Abstract

Based a new empirical mobility model that's solely dependent on V gs , V t , and T or and a corresponding saturation drain current (I dsat ) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V dd (for low power applications) if V t can be lowered.

Original languageEnglish
Pages (from-to)202-204
Number of pages3
JournalIEEE Electron Device Letters
Volume17
Issue number5
DOIs
StatePublished - 1 May 1996

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