The guideline on designing face-tunneling FET for large-scale-device applications in IoT

E. R. Hsieh*, J. W. Lee, M. H. Lee, Steve S. Chung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0 of f-TFET with one-order magnitude In enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control and shows strong dependency on temperature because of dominance of trap-assisted tunneling. To understand how traps affect Ion of f-TFET, the charge-pumping measurement is utilized to examine trap distributions in the tunneling region. The results show that the channel/source interfacial traps degrade the performance of f-TFET, however, with careful treatment of the epi-process of f-TFET, this device with face-tunneling shows great potential for future IoT applications.

Original languageEnglish
Title of host publication2017 Silicon Nanoelectronics Workshop, SNW 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Electronic)9784863486478
DOIs
StatePublished - 29 Dec 2017
Event22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, Japan
Duration: 4 Jun 20175 Jun 2017

Publication series

Name2017 Silicon Nanoelectronics Workshop, SNW 2017
Volume2017-January

Conference

Conference22nd Silicon Nanoelectronics Workshop, SNW 2017
CountryJapan
CityKyoto
Period4/06/175/06/17

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  • Cite this

    Hsieh, E. R., Lee, J. W., Lee, M. H., & Chung, S. S. (2017). The guideline on designing face-tunneling FET for large-scale-device applications in IoT. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 1-2). [8242268] (2017 Silicon Nanoelectronics Workshop, SNW 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/SNW.2017.8242268