The generalized delay time and crosstalk models for the interconnect optimization design

Trent Gwo Yann Lee*, Tseung-Yuen Tseng, Shyh Chyi Wong, Cheng Jer Yang, Mong Song Liang, Huang-Chung Cheng

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

New analytical models for estimating the delay time and crosstalk voltage with ramp input for isolated single line and coupled interconnect are presented here. Normal and crosstalk induced delay time deterioration and worst-case crosstalk noise models are given and verified by SPICE simulation. These models are accurate for various driver resistances, loading capacitances, and ramp waveforms. This paper is useful in the interconnect optimization design, the studies of delay time uncertainty due to noise and interconnect design in the worst case.

Original languageAmerican English
Pages291-294
Number of pages4
StatePublished - 1 Dec 2001
Event9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems - Singapore, Singapore
Duration: 3 Sep 20015 Sep 2001

Conference

Conference9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems
CountrySingapore
CitySingapore
Period3/09/015/09/01

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