The effect of gate recess profile on device performance of Ga0.51in0.49P/In0.2Ga0.8as doped-channel FET's

Shey Shi Lu*, Chin-Chun Meng, Yo Sheng Lin, Hai Lan

*Corresponding author for this work

Research output: Contribution to journalArticle

22 Scopus citations

Abstract

The effect of gate recess profile on device performance of Ga0.51In0.4gP/In0.2Gao.sAs doped-channel FET's was studied. In the experiment, Ga0.51In0.4gP/In0.2Gao.sAs dopedchannel FET's (DCFET's) using triple-recessed gate structure were compared with devices using single-recessed and doublerecessed gate structures. It is found that triple-recessed gate approach provides higher breakdown voltage (35 V) than singlerecessed (16 V) and double-recessed gate (28 V) approaches. This is attributed to the larger aspect ratio in the triple-recessed gate structure. A unified method to calculate the breakdown voltages of MESFET's, HEMT's and DCFET's (or MISFET's) of any given arbitrary recessed gate profile was proposed and used to explain the experimental results.

Original languageEnglish
Pages (from-to)48-54
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume46
Issue number1
DOIs
StatePublished - 1 Dec 1999

Keywords

  • Breakdown voltage
  • Doped-channel fet
  • Galnp
  • Gate recess

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