The development of the next generation BSIM for sub-100nm mixed-signal circuit simulation

Xuemei Xi*, Jin He, Mohan Dunga, Chung Hsun Lin, Babak Heydari, Hui Wan, Mansun Chan, Ali M. Niknejad, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper describes the next generation BSIM model for aggressively scaled CMOS technology. New features in the model include more accurate non-charge-sheet based physics, completely continuous current and derivatives, and extendibility to non-traditional CMOS based devices including SOI and double-gate MOSFETs.

Original languageEnglish
Title of host publication2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
EditorsM. Laudon, B. Romanowicz
Pages70-73
Number of pages4
StatePublished - 2 Nov 2004
Event2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States
Duration: 7 Mar 200411 Mar 2004

Publication series

Name2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Volume2

Conference

Conference2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
CountryUnited States
CityBoston, MA
Period7/03/0411/03/04

Keywords

  • Compact modeling
  • MOSFETs
  • Small dimensional effects
  • Surface-potential-plus model

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