The design of low-power CIFF structure second-order sigma-delta modulator

Pin Han Su*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-μm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.

Original languageEnglish
Title of host publication2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
Pages377-380
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09 - Cancun, Mexico
Duration: 2 Aug 20095 Aug 2009

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference2009 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09
CountryMexico
CityCancun
Period2/08/095/08/09

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