TY - JOUR
T1 - The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current-mode processing techniques
AU - Liow, Yu Y.
AU - Wu, Chung-Yu
PY - 2002/1/1
Y1 - 2002/1/1
N2 - In this paper, a new structure of 8-bit CMOS pipelined analog-to-digital converter (ADC) is proposed and analyzed. In order to achieve a high conversion rate, the proposed new structure adopts voltage-mode open-loop sampling circuit and current-mode circuits to perform subtraction, sub-DAC operation, and comparison. Due to current-mode subtraction operation, the close-loop circuit can be avoided to improve the speed performance. Moreover, current steering sub-DAC is used to enhance the sub-DAC speed. From the simulation results on the demonstrative example, the proposed pipelined ADC architecture can achieve 8-bit accuracy with a sampling rate up to 71.4MS/s when the input signal frequency is 10M Hz. The power dissipation of the pipelined ADC is 205mW at the conversion rate of 71.4 MS/s with a single 3.3V power supply and 1P5M 0.25μm CMOS process. The proposed structure can reach a higher speed if the voltage-sampling delay is reduced.
AB - In this paper, a new structure of 8-bit CMOS pipelined analog-to-digital converter (ADC) is proposed and analyzed. In order to achieve a high conversion rate, the proposed new structure adopts voltage-mode open-loop sampling circuit and current-mode circuits to perform subtraction, sub-DAC operation, and comparison. Due to current-mode subtraction operation, the close-loop circuit can be avoided to improve the speed performance. Moreover, current steering sub-DAC is used to enhance the sub-DAC speed. From the simulation results on the demonstrative example, the proposed pipelined ADC architecture can achieve 8-bit accuracy with a sampling rate up to 71.4MS/s when the input signal frequency is 10M Hz. The power dissipation of the pipelined ADC is 205mW at the conversion rate of 71.4 MS/s with a single 3.3V power supply and 1P5M 0.25μm CMOS process. The proposed structure can reach a higher speed if the voltage-sampling delay is reduced.
UR - http://www.scopus.com/inward/record.url?scp=0036290747&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2002.1010174
DO - 10.1109/ISCAS.2002.1010174
M3 - Conference article
AN - SCOPUS:0036290747
VL - 3
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
Y2 - 26 May 2002 through 29 May 2002
ER -