The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions

Steve S. Chung, E. R. Hsieh, Y. B. Zhao, J. W. Lee, M. H. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its I on current. This work shows I on of f-TFET with one-order magnitude I on enhancement than that of point-TFET(control), and the longer the gate length is, the higher the I on becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.

Original languageEnglish
Title of host publication2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538662342
DOIs
StatePublished - 9 Oct 2018
Event2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018 - Shenzhen, China
Duration: 6 Jun 20188 Jun 2018

Publication series

Name2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018

Conference

Conference2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
CountryChina
CityShenzhen
Period6/06/188/06/18

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