The design of a K-Band 0.8-V 9.2-mW phase-locked loop

Zue Der Huang*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-μm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and currentinjection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is .98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is .69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

Original languageEnglish
Pages (from-to)1289-1294
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE94-C
Issue number8
DOIs
StatePublished - 1 Jan 2011

Keywords

  • Complementary-type charge pump
  • Coupling current-mode injection-locked frequency divider (CCMILFD)
  • Phase-locked loop (PLL)
  • SPR-PFD
  • VCO

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