The Analysis and Design of CMOS Multidrain Logic and Stacked Multidrain Logic

Chung-Yu Wu*, Jinn Shyan Wang, Ming Kai Tsai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

A new CMOS logic called the CMOS multidrain logic (MDL) is analyzed and investigated. Its basic structure consists of one MOS current injector which is connected to the input node, and one multidrain MOS driver with its drains as outputs and its gate as input. There are four available configurations in the static CMOS MDL. Each configuration can conveniently form a wire-and or wire-or function by tying the output drain nodes together. Both multidrain and wire-logic capabilities lead to a smaller average area per gate than that of the conventional CMOS logic. From transient analysis results, it is seen that the speed of the static CMOS MDL is comparable to that of I2L or even ECL and is about 20–70 percent better than that of the conventional CMOS logic, whereas the power-delay product is smaller than that of I2L and ECL and is nearly the same as CMOS under 300-MHz operation. Therefore, by using the static CMOS MDL, the speed performance can be promoted without any degradation in power-delay product or packing density. In dynamic circuits, a new structure called the dynamic CMOS stacked MDL (SMDL) is formed by stacking the MDL circuits. Due to the inherent multidrain connections, various Boolean terms are realizable within a highly merged dynamic SMDL gate. Therefore the dynamic CMOS SMDL has the features of high packing density and low interconnection complexity which make it a potential technique in CMOS VLSI design.

Original languageEnglish
Pages (from-to)47-56
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number1
DOIs
StatePublished - 1 Jan 1987

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