The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.
|Number of pages||4|
|Journal||European Solid-State Circuits Conference|
|State||Published - 24 Sep 2002|
|Event||28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy|
Duration: 24 Sep 2002 → 26 Sep 2002