The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh; Jeffrey Draper; Sumit Mediratta; Jeff Sondeen

The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh, Jeffrey Draper, Sumit Mediratta, Jeff Sondeen

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

Original language	English
Article number	1471640
Pages (from-to)	767-770
Number of pages	4
Journal	European Solid-State Circuits Conference
State	Published - 24 Sep 2002
Event	28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy Duration: 24 Sep 2002 → 26 Sep 2002

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title = "The address translation unit of the data-intensive architecture (DIVA) system",

abstract = "The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.",

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AU - Draper, Jeffrey

AU - Mediratta, Sumit

AU - Sondeen, Jeff

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AB - The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

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M3 - Conference article

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SN - 1930-8833

M1 - 1471640

Y2 - 24 September 2002 through 26 September 2002

ER -

The address translation unit of the data-intensive architecture (DIVA) system

Abstract

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