The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh; Jeffrey Draper; Sumit Mediratta; Jeff Sondeen

The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh, Jeffrey Draper, Sumit Mediratta, Jeff Sondeen

National Chiao Tung University

Research output: Contribution to journal › Conference article

3 Scopus citations

Abstract

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

Original language	English
Article number	1471640
Pages (from-to)	767-770
Number of pages	4
Journal	European Solid-State Circuits Conference
State	Published - 1 Dec 2002
Event	28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy Duration: 24 Sep 2002 → 26 Sep 2002

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Chiueh, H-M., Draper, J., Mediratta, S., & Sondeen, J. (2002). The address translation unit of the data-intensive architecture (DIVA) system. European Solid-State Circuits Conference, 767-770. [1471640].

@article{60f2252a2d6c4e57ba99e0d9cf5c5c6c,

title = "The address translation unit of the data-intensive architecture (DIVA) system",

abstract = "The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.",

author = "Her-Ming Chiueh and Jeffrey Draper and Sumit Mediratta and Jeff Sondeen",

year = "2002",

month = dec,

day = "1",

language = "English",

pages = "767--770",

journal = "European Solid-State Circuits Conference",

issn = "1930-8833",

note = "null ; Conference date: 24-09-2002 Through 26-09-2002",

}

TY - JOUR

T1 - The address translation unit of the data-intensive architecture (DIVA) system

AU - Chiueh, Her-Ming

AU - Draper, Jeffrey

AU - Mediratta, Sumit

AU - Sondeen, Jeff

PY - 2002/12/1

Y1 - 2002/12/1

N2 - The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

AB - The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

UR - http://www.scopus.com/inward/record.url?scp=84893720979&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:84893720979

SP - 767

EP - 770

JO - European Solid-State Circuits Conference

JF - European Solid-State Circuits Conference

SN - 1930-8833

M1 - 1471640

Y2 - 24 September 2002 through 26 September 2002

ER -