The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh, Jeffrey Draper, Sumit Mediratta, Jeff Sondeen

Research output: Contribution to journalConference article

3 Scopus citations

Abstract

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

Original languageEnglish
Article number1471640
Pages (from-to)767-770
Number of pages4
JournalEuropean Solid-State Circuits Conference
StatePublished - 1 Dec 2002
Event28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy
Duration: 24 Sep 200226 Sep 2002

Fingerprint Dive into the research topics of 'The address translation unit of the data-intensive architecture (DIVA) system'. Together they form a unique fingerprint.

  • Cite this