Testing strategies for a 9T sub-threshold SRAM

Hao Yu Yang*, Chen Wei Lin, Hung Hsin Chen, Chia-Tso Chao, Ming Hsien Tu, Shyh-Jye Jou, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.

Original languageEnglish
Title of host publicationITC 2012 - International Test Conference 2012, Proceedings
DOIs
StatePublished - 1 Dec 2012
Event2012 International Test Conference, ITC 2012 - Anaheim, CA, United States
Duration: 6 Nov 20128 Nov 2012

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

Conference2012 International Test Conference, ITC 2012
CountryUnited States
CityAnaheim, CA
Period6/11/128/11/12

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