Testing retention flip-flops in power-gated designs

Hao Wen Hsu, Shih Hua Kuo, Wen Hsiang Chang, Shi Hao Chen, Ming Tung Chang, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs
StatePublished - 14 Aug 2013
Event2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
Duration: 29 Apr 20131 May 2013

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
CountryUnited States
CityBerkeley, CA
Period29/04/131/05/13

Fingerprint Dive into the research topics of 'Testing retention flip-flops in power-gated designs'. Together they form a unique fingerprint.

  • Cite this

    Hsu, H. W., Kuo, S. H., Chang, W. H., Chen, S. H., Chang, M. T., & Chao, C-T. (2013). Testing retention flip-flops in power-gated designs. In Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013 [6548880] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2013.6548880