Testing methods for a write-assist disturbance-free dual-port SRAM

Hao Yu Yang, Chen Wei Lin, Chao Ying Huang, Ching Ho Lu, Chen An Lai, Chia-Tso Chao, Rei Fu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new write-assist dual-port SRAM proposed in [10] by using a 28nm LP process and then discussed the faulty behavior of injecting different resistive-open defects into both the SRAM cell and write-assist circuit. Next, we developed new test methods to detect the hard-to-detect resistive-open defects and proposed a corresponding March-like algorithm that covers a widely used March C- as well as the proposed test methods. Last, the required DfT for the proposed test methods was also discussed.

Original languageEnglish
Title of host publicationProceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014
PublisherIEEE Computer Society
ISBN (Print)9781479926114
StatePublished - 1 Jan 2014
Event2014 IEEE 32nd VLSI Test Symposium, VTS 2014 - Napa, CA, United States
Duration: 13 Apr 201417 Apr 2014

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2014 IEEE 32nd VLSI Test Symposium, VTS 2014
CountryUnited States
CityNapa, CA

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