Testing methodology of embedded DRAMs

Hao Yu Yang*, Chi Min Chang, Chia-Tso Chao, Rei Fu Huang, Shih Chin Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

12 Scopus citations

Abstract

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

Original languageEnglish
Article number5981413
Pages (from-to)1715-1728
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number9
DOIs
StatePublished - 1 Jan 2012

Keywords

  • Embedded-DRAM (eDRAM)
  • error-correction-code
  • fault model
  • retention

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