Testable design and testing of MCMs based on multifrequency scan

Wang Dauh Tseng*, Kuo-Chen Wang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations


In this paper, we present a novel and efficient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to offer the necessity of controllability and observability. Part of the boundary scan cells used in the chip level are modified to form the module level scan chain. Using the chip level boundary scan cells to provide both chip and module level testings, it not only decreases area overhead but also reduces extra delay introduced by the addition of test circuits. The contribution of this paper is to provide an MCM design for testability strategy which has the capability to detect performance defects as well as static faults will small delay and low overhead.

Original languageEnglish
Pages (from-to)75-80
Number of pages6
JournalProceedings of the Asian Test Symposium
StatePublished - 1 Dec 1996
EventProceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan
Duration: 20 Nov 199622 Nov 1996

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