Test structure on SCR device in waffle layout for RF ESD protection

Ming-Dou Ker*, Chun Yu Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.

Original languageEnglish
Title of host publication2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
Pages196-199
Number of pages4
DOIs
StatePublished - 27 Sep 2007
Event2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, Japan
Duration: 19 Mar 200722 Mar 2007

Publication series

NameIEEE International Conference on Microelectronic Test Structures

Conference

Conference2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
CountryJapan
CityBunkyo-ku
Period19/03/0722/03/07

Keywords

  • Electrostatic discharges (ESD)
  • Radio-frequency integrated circuit (RF IC)
  • Silicon-controlled rectifier (SCR)

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