High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg=- Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.
|Number of pages||3|
|State||Published - 1 Jan 2002|
|Event||IEEE International SOI Conference - Williamsburg, VA, United States|
Duration: 7 Oct 2002 → 10 Oct 2002
|Conference||IEEE International SOI Conference|
|Period||7/10/02 → 10/10/02|