Tendency for full depletion due to gate tunneling current

Hui Wan*, Samuel K H Fung, Pin Su, Mansun Chan, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaper

6 Scopus citations


High gate tunneling current level from ultra-thin gate dielectric leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg=- Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.

Original languageEnglish
Number of pages3
StatePublished - 1 Jan 2002
EventIEEE International SOI Conference - Williamsburg, VA, United States
Duration: 7 Oct 200210 Oct 2002


ConferenceIEEE International SOI Conference
CountryUnited States
CityWilliamsburg, VA

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