Different degradation modes were observed under high and low reverse stress current conditions. The temperature dependence of the degradation was studied, and it was found that the degradation is greatest around 50°C. The mechanisms of the degradation and its recovery were also investigated, using MOS structures and simulation. MOSFET evaluation indicated that electron trapping and interface state generation occur during the stress. Simulation confirmed that the degradation is caused mainly by the interface states generated in the oxide near the emitter-base junction.
|Number of pages||4|
|State||Published - 1989|
|Event||Proceedings of the 1989 Bipolar Circuits and Technology Meeting - Minneapolis, MN, USA|
Duration: 18 Sep 1989 → 19 Sep 1989
|Conference||Proceedings of the 1989 Bipolar Circuits and Technology Meeting|
|City||Minneapolis, MN, USA|
|Period||18/09/89 → 19/09/89|