Many technology and reliability challenges emerge as we continue to push Moore's Law. On the lithography front, ArF 193nm liquid-immersion lithography offers great promise to provide us with cost-effective manufacturing solutions to the 32nm generation. Transistor and interconnect scaling require new materials and structures that may not be conventional in the nanometer regime, e.g., strained-Si channel, high-K gate dielectric, metal gate, non-bulk or no-planar CMOS structures, low-K interconnects, and many SoC-enabling features. The unrelenting pressure to reduce die cost and manufacturing cycle time, while accelerating the time to market and the time to volume adds additional challenges. Foundry is in a unique position to work with the rest of the industry to overcome these challenges and provide cost-effective solutions in a collaborative and virtually integrated way. New methodology, infrastructure, circuit design, and system architecture solutions are needed for all phases and aspects of the technology development, qualification, and manufacturing, e.g., modeling, characterization, failure analysis, concurrent process and reliability engineering, design for manufacturing, and design for test/debug.
|Number of pages||4|
|State||Published - 2004|
|Event||Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan|
Duration: 5 Jul 2004 → 8 Jul 2004
|Conference||Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004|
|Period||5/07/04 → 8/07/04|