Technologies Toward Three-Dimensional Brain-Mimicking IC Architecture

Albert Chin*, You Da Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Although device downscaling will soon reach the quantum limit, the speed and power are still the hard challenges for advanced ICs. To address these speed and power issues, we pioneered the three-dimensional (3D) IC in 2004. In contrast to few interconnects of package-level 3D IC, device-level high-mobility nMOS on VLSI backend, unipolar nMOS logic with CMOS-like ultra-low DC power, narrow distribution RRAM, and high-speed ferroelectric nMOS memory are the enabling technologies toward brain-mimicking IC architecture.

Original languageEnglish
Title of host publication2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages472-474
Number of pages3
ISBN (Electronic)9781538665084
DOIs
StatePublished - Mar 2019
Event2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 - Singapore, Singapore
Duration: 12 Mar 201915 Mar 2019

Publication series

Name2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019

Conference

Conference2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
CountrySingapore
CitySingapore
Period12/03/1915/03/19

Keywords

  • device level 3D
  • memory
  • unipolar logic

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  • Cite this

    Chin, A., & Chen, Y. D. (2019). Technologies Toward Three-Dimensional Brain-Mimicking IC Architecture. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 (pp. 472-474). [8731323] (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2019.8731323